Candidate will be responsible for defining the verification test plan for a sub-system or IP integration verification at full chip. Candidate needs to code test cases, and associated checkers/assertions, simulation/debug of test cases in RTL, power aware and Gate level simulations. Shall be responsible for review and closure of toggle coverage for IPs. Verification environment […]
This position is for Physical Design and Timing Closure of complex, low power SoCs targeted for IOT and MCU markets. Candidate will be responsible to drive die area, performance, power goals during physical design implementation. Candidate will work on various stages of physical design implementation which includes floorplanning, power grid design, place and route, clock […]
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