Sr Staff Elec. Design Engg Updated On Tue, May 17th, 2022 by Saurenergy Must have successfully developed multiple Si Proven IP from spec to production Must have deep understanding with IP development methodology and Chip level analog macro integration Experience with Cadence, Eldo, Finesim, Questa ADMS, HSPICE or equivalent tools required Good understanding of analog macros such as ADC/DAC, PLL, Oscillator, Bandgap, Comparator, Buck/Boost, LDO, Type-C and Process […] Read more
