Staff Engineer Elect Design

• Candidate will be responsible for defining the verification test plan for a sub-system or IP integration verification at full chip.
• Candidate needs to code test cases, and associated checkers/assertions, simulation/debug of test cases in RTL, power aware and Gate level simulations.
• Shall be responsible for review and closure of toggle coverage for IPs.
• Verification environment shall be SV/UVM based and has C+SV based test cases.

MUST have:-

• Good understanding of ASIC logic verification concepts and techniques.
• Ability to develop complex full chip test cases and should have sharp debugging skills.
• Ability to understand design aspects of multi power domain SoC, and able to define and execute complex chip level power mode transitions thoroughly verifying the power mode interdependencies between IPs.

Your Profile:-

• Very good knowledge of Verilog/System Verilog and UVM.
• Must have good understanding of AHB/APB/AHB5/AXI4 bus protocols
• Experience on ARM microcontroller based multi-core SoCs, and prior experience with a C+SV based verification environment is preferred.
• Experience with developing re-usable verification components/tests, to support parameterized design verification.
• Expertise on RTL+UPF based power aware verification is preferred.
• Gate level simulation/debug expertise is a plus.
• Exposure to deployment of automation and formal verification methodologies is a plus

Location:-

• Bangalore, India.

Company Overview:-

Infineon Technologies AG is a world leader in semiconductor solutions that make life easier, safer and greener. Microelectronics from Infineon are the key to a better future. In the 2020 fiscal year (ending 30 September), Infineon reported revenue of more than €8.5 billion with a workforce of some 46,700 people worldwide. Following the acquisition of the US company Cypress Semiconductor Corporation in April 2020, Infineon is now a global top 10 semiconductor company.